1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a method and structure for reducing intralevel capacitive coupling between adjacent conductors in areas of dense circuitry by staggering an intermediate conductor with respect to its adjacent conductors.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a "bus". A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric material. Accordingly, the layers of conductors overlaid with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material, a suitable material includes Cu, Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate is a silicon-based material which receives p-type or n-type ions.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and spaced above an underlying conductor or substrate by a dielectric of thickness T.sub.d1. Each conductor is dielectrically spaced from other conductors within the same level of conductors by a distance T.sub.d2. Accordingly, interlevel capacitance C.sub.LS (i.e., capacitance between conductors on different levels) is determined as follows: EQU C.sub.LS .apprxeq..epsilon.W.sub.L L/T.sub.d1 (Eq. 1)
Further, the intralevel capacitance C.sub.LL (i.e., capacitance between conductors on the same level) is determined as follows: EQU C.sub.LL .apprxeq..epsilon.T.sub.c L/T.sub.d2 (Eq. 2)
, where .epsilon. is the permittivity of the dielectric material (the dielectric material between the conductor and substrate or the dielectric material between conductors), W.sub.L is the conductor width, T.sub.c is the conductor thickness, and L is the conductor length. Resistance of the conductor is calculated as follows: EQU R=(.rho.L)/W.sub.L T.sub.c (Eq. 3)
, where .rho. represents resistivity of the conductive material, and T.sub.c is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate the propagation delay of a conductor as follows: EQU RC.sub.LS .apprxeq..rho..epsilon.L.sup.2 /T.sub.c T.sub.d1 EQU RC.sub.LL .apprxeq..rho..epsilon.L.sup.2 /W.sub.L T.sub.d2 (Eq. 4)
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay be minimized as much as possible within the geometric constraints of the semiconductor topography.
Equation 4 shows that the propagation delay of a circuit is determined by parasitic capacitance values (C.sub.LL) between laterally spaced conductors, and parasitic capacitance values (C.sub.LS) between vertically spaced conductors or between a conductor and the underlying substrate. As circuit density increases, lateral spacing and vertical spacing between conductors decrease and capacitance C.sub.LL increases. Meanwhile, planarization mandates to some extent a decrease in vertical spacing. Shallow trench processing, recessed LOCOS processing, and multi-layered interlevel dielectrics bring about an overall reduction in vertical spacing and therefore an increase in C.sub.LS. Integrated circuits which employ narrow interconnect spacings thereby define C.sub.LL as a predominant capacitance, and integrated circuits which employ thin interlevel dielectrics define C.sub.LS as a predominant capacitance.
Increases in C.sub.LL or C.sub.LS parasitic capacitance pose two major problems. First, an increase in parasitic capacitance generally causes an increase in the time at which a transition on the one end of the conductor occurs at the other end. Increased transition time slows circuit operation because a longer drive period is required to allow the entire conductor to achieve a steady state value. If the conductor extends along a critical speed path, speed degradation on the line will jeopardize functionality of the overall circuit. Second, a larger parasitic capacitance causes an increase in crosstalk noise. A conductor which does not transition, nonetheless receives crosstalk noise from neighboring lines which do.
It is therefore important to minimize propagation delay especially in critical speed paths. FIGS. 1 and 2 show a partial top plan view and a partial cross-sectional view, respectively, of a conventional dual level interconnect structure. A plurality of first conductors 10 is arranged across semiconductor substrate 8 to form a first interconnect level. Substrate 8 is defined to include a dielectric, upon which interconnect is patterned and selectively linked, possibly through openings within the dielectric. Subsequent to formation of an interconnect, dielectric layer 11 is formed upon first interconnect level 10. A plurality of second conductors 12 is then arranged upon first dielectric layer 11 to form second interconnect level 13. Regions 14 of dense circuitry occur in second interconnect level 13 wherever a plurality of second conductors 12 come in close proximity to each other. As seen more clearly in FIG. 2, the horizontal displacement between adjacent second conductors 12, shown as d.sub.h1, can be significantly greater than the vertical displacement, d.sub.v1, between first interconnect level 10 and second interconnect level 13. When d.sub.h1 is significantly less than d.sub.v1, intralevel capacitance C.sub.LL tends to dominate circuit performance. Stated similarly, control and minimization of intralevel capacitance CLL becomes increasingly significant as the horizontal displacement between adjacent conductors decreases. Given the constraints of chemical compositions, it is not readily plausible to reduce the resistivity .rho. of conductor materials nor the permittivity .epsilon. of conventional interlevel dielectrics such as CVD (chemical vapor deposition) oxides. Processing constraints make it difficult to increase conductor thickness T.sub.c or dielectric thickness T.sub.d1 or T.sub.d2. Still further, instead of reducing length L of a conductor, most modern integrated circuits employ long interconnect lines which compound the propagation delay problems. Accordingly, a need arises for instituting a reduction in propagation delay and cross talk noise within the constraints of existing fabrication processes.